I. Field of the Invention
The present invention relates to the field of imaging. More precisely, the present invention relates to pixels of image sensors.
II. Background of the Invention
Imaging arrays, used to produce images representing objects, are typically formed of rows and columns (bitlines) of photo detectors (pixels). The pixels generate photo charges proportional to light reflected from an object to be imaged. Photo charges from each pixel are converted to a signal (charge signal) or potential representative of a level of energy reflected from a respective portion of the object. The signal or potential is read and processed by video processing circuitry to create an image representing an object.
Pixels belonging to a same bitline are usually connected at a common output node from where a signal or potential, representative of the level of energy, is read out. Pixels belonging to the same bitline xe2x80x9cseexe2x80x9d an overall capacitance (hereinafter referred to as xe2x80x9cbitline capacitancexe2x80x9d), at the common output node. Each pixel in a same bitline is individually controlled to read out at the common output node. Typically, pixels belonging to a same row are commonly controlled by a same signal (wordline) such that an entire row may be read out at a substantially same time.
To meet the increasing need for high speed image sensor devices, image sensor arrays are integrated with digital circuitry that controls the operation of the array and processes the array""s output. Integration of image sensors with complementary-metal-oxide-semiconductor (CMOS) support circuitry is most desirable because of the low power consumption characteristics and common availability of CMOS technology. Such an imaging array integrated with CMOS support circuitry is called CMOS active pixel sensor (APS) array.
Typically, a pixel includes a photosensor that detects light impinging thereon and xe2x80x9cconvertsxe2x80x9d the light into an electronic signal indicative of an intensity of light detected by the pixel. A driving device receives the electronic signal and drives a current proportional to the electronic signal to a bitline to which the pixel is coupled. Then the pixels in a selected row are accessed by asserting the WORDLINE signal to each pixel access device of each pixel cell of a selected row. Then each bitline to which a corresponding pixel of the selected row is coupled, may be charged by a current driven by the driving device of the pixel to a voltage level representative of an intensity of light detected by that pixel. The pixels of an entire row may thus be read out at a substantially same time. The pixel cells of other rows, not currently accessed, have their pixel access devices switched off by deasserting the wordline signals corresponding to these rows.
One of the problems in active image sensor arrays is offset. Offset in the voltage readout from the pixel may be due to leakage and offset in the read out circuit (source follower), correlated double sampling, and analog-to-digital converter. FIG. 1 is a diagram that illustrates several waveforms representing the output signal of a pixel of a CMOS sensor array. Waveform 102 represents the output voltage in an ideal case where offset is not present. Waveform 104 is a waveform representing the output voltage where an offset Voff is present. The offset may be amplified by a gain stage giving rise to waveform 106. Note that, since the voltage range for waveform 104 is positive, so will be the voltage range for waveform 106. The offset therefore causes a reduction in the output swing and thereby a reduction in a dynamic range.
In one embodiment, the present invention includes a circuit for offset reduction in an active pixel sensor array. The circuit includes a voltage regulator to regulate a reset voltage at an output port of the voltage regulator for a pixel of the active pixel sensor array. The circuit further includes at least one programmable circuit, coupled to the voltage regulator, to adjust the reset voltage and reduce the offset by a first value.